Concurrent All-Cell Error Detection in Semi-Systolic Multiplier Using Linear Codes

Finite field multiplier is widely applied in many domains such as coding theory and cryptography. In this paper, it is purposed to propose a concurrent all-cell error detection semi-systolic polynomial basis multiplier based on coding theory which can realize high-speed calculation and high efficient error detection with low resource consumption. First, our method is created to choose an appreciate generator polynomial for a linear code and an irreducible polynomial generating the finite field. Then the finite field arithmetic multiplication with error detection is simplified on a residue class ring resulted from linearly coding. Second, a semi-systolic array is compressed to realize our multiplier which is suitable for almost any finite field with low time and area complexity. Furthermore, our method breaks through the key technical bottleneck of unacceptable time and area overheads in the coding, decoding and checking process. Additionally, the paper creatively builds an all-cell error model for systolic or semi-systolic multipliers more practical than the conventional single stuck-at or single-cell error model. Finally, based on the all-cell error model, the proposed multiplier is only with 2.088% extra time overhead and 4.978% extra area overhead, and its probability of concurrent error detection reaches to 99.999999%.